/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
 * Copyright 2020-2023 NXP
 */
#ifndef __DT_BINDINGS_SCMI_CLOCK_S32CC_H
#define __DT_BINDINGS_SCMI_CLOCK_S32CC_H

#define S32CC_SCMI_CLK_BASE_ID		0U
#define S32CC_SCMI_CLK(N)		((N) + S32CC_SCMI_CLK_BASE_ID)
#define S32CC_PLAT_SCMI_CLK(N)		((N) + S32CC_SCMI_PLAT_CLK_BASE_ID)

/* A53 */
#define S32CC_SCMI_CLK_A53			S32CC_SCMI_CLK(0)
/* SERDES */
#define S32CC_SCMI_CLK_SERDES_AXI		S32CC_SCMI_CLK(1)
#define S32CC_SCMI_CLK_SERDES_AUX		S32CC_SCMI_CLK(2)
#define S32CC_SCMI_CLK_SERDES_APB		S32CC_SCMI_CLK(3)
#define S32CC_SCMI_CLK_SERDES_REF		S32CC_SCMI_CLK(4)
#define S32CC_SCMI_CLK_SERDES_PAD_REF		S32CC_SCMI_CLK(5)
/* FTM0 */
#define S32CC_SCMI_CLK_FTM0_SYS			S32CC_SCMI_CLK(6)
#define S32CC_SCMI_CLK_FTM0_EXT			S32CC_SCMI_CLK(7)
/* FTM1 */
#define S32CC_SCMI_CLK_FTM1_SYS			S32CC_SCMI_CLK(8)
#define S32CC_SCMI_CLK_FTM1_EXT			S32CC_SCMI_CLK(9)
/* FlexCAN */
#define S32CC_SCMI_CLK_FLEXCAN_REG		S32CC_SCMI_CLK(10)
#define S32CC_SCMI_CLK_FLEXCAN_SYS		S32CC_SCMI_CLK(11)
#define S32CC_SCMI_CLK_FLEXCAN_CAN		S32CC_SCMI_CLK(12)
#define S32CC_SCMI_CLK_FLEXCAN_TS		S32CC_SCMI_CLK(13)
/* LINFlexD */
#define S32CC_SCMI_CLK_LINFLEX_XBAR		S32CC_SCMI_CLK(14)
#define S32CC_SCMI_CLK_LINFLEX_LIN		S32CC_SCMI_CLK(15)
#define S32CC_SCMI_CLK_GMAC0_TS			S32CC_SCMI_CLK(16)
/* GMAC0 - SGMII */
#define S32CC_SCMI_CLK_GMAC0_RX_SGMII		S32CC_SCMI_CLK(17)
#define S32CC_SCMI_CLK_GMAC0_TX_SGMII		S32CC_SCMI_CLK(18)
/* GMAC0 - RGMII */
#define S32CC_SCMI_CLK_GMAC0_RX_RGMII		S32CC_SCMI_CLK(19)
#define S32CC_SCMI_CLK_GMAC0_TX_RGMII		S32CC_SCMI_CLK(20)
/* GMAC0 - RMII */
#define S32CC_SCMI_CLK_GMAC0_RX_RMII		S32CC_SCMI_CLK(21)
#define S32CC_SCMI_CLK_GMAC0_TX_RMII		S32CC_SCMI_CLK(22)
/* GMAC0 - MII */
#define S32CC_SCMI_CLK_GMAC0_RX_MII		S32CC_SCMI_CLK(23)
#define S32CC_SCMI_CLK_GMAC0_TX_MII		S32CC_SCMI_CLK(24)
#define S32CC_SCMI_CLK_GMAC0_AXI		S32CC_SCMI_CLK(25)
/* SPI */
#define S32CC_SCMI_CLK_SPI_REG			S32CC_SCMI_CLK(26)
#define S32CC_SCMI_CLK_SPI_MODULE		S32CC_SCMI_CLK(27)
/* QSPI */
#define S32CC_SCMI_CLK_QSPI_REG			S32CC_SCMI_CLK(28)
#define S32CC_SCMI_CLK_QSPI_AHB			S32CC_SCMI_CLK(29)
#define S32CC_SCMI_CLK_QSPI_FLASH2X		S32CC_SCMI_CLK(30)
#define S32CC_SCMI_CLK_QSPI_FLASH1X		S32CC_SCMI_CLK(31)
/* uSDHC */
#define S32CC_SCMI_CLK_USDHC_AHB		S32CC_SCMI_CLK(32)
#define S32CC_SCMI_CLK_USDHC_MODULE		S32CC_SCMI_CLK(33)
#define S32CC_SCMI_CLK_USDHC_CORE		S32CC_SCMI_CLK(34)
/* I2C */
#define S32CC_SCMI_CLK_I2C_REG			S32CC_SCMI_CLK(41)
#define S32CC_SCMI_CLK_I2C_MODULE		S32CC_SCMI_CLK(42)
/* FCCU */
#define S32CC_SCMI_CLK_FCCU_MODULE		S32CC_SCMI_CLK(53)
#define S32CC_SCMI_CLK_FCCU_SAFE		S32CC_SCMI_CLK(54)
/* RTC */
#define S32CC_SCMI_CLK_RTC_REG			S32CC_SCMI_CLK(55)
#define S32CC_SCMI_CLK_RTC_SIRC			S32CC_SCMI_CLK(56)
#define S32CC_SCMI_CLK_RTC_FIRC			S32CC_SCMI_CLK(57)
/* SWT */
#define S32CC_SCMI_CLK_SWT_MODULE		S32CC_SCMI_CLK(58)
#define S32CC_SCMI_CLK_SWT_COUNTER		S32CC_SCMI_CLK(59)
/* STM */
#define S32CC_SCMI_CLK_STM_MODULE		S32CC_SCMI_CLK(60)
#define S32CC_SCMI_CLK_STM_REG			S32CC_SCMI_CLK(61)
/* PIT */
#define S32CC_SCMI_CLK_PIT_MODULE		S32CC_SCMI_CLK(62)
#define S32CC_SCMI_CLK_PIT_REG			S32CC_SCMI_CLK(63)
/* eDMA */
#define S32CC_SCMI_CLK_EDMA_MODULE		S32CC_SCMI_CLK(64)
#define S32CC_SCMI_CLK_EDMA_AHB			S32CC_SCMI_CLK(65)
/* SAR-ADC */
#define S32CC_SCMI_CLK_SAR_ADC_BUS		S32CC_SCMI_CLK(66)
/* TMU */
#define S32CC_SCMI_CLK_TMU_MODULE		S32CC_SCMI_CLK(69)
#define S32CC_SCMI_CLK_TMU_REG			S32CC_SCMI_CLK(70)

#define S32CC_SCMI_PLAT_CLK_BASE_ID		S32CC_SCMI_CLK(71)

#endif /* __DT_BINDINGS_SCMI_CLOCK_S32CC_H */
